In monolithic memories, several storage cells are formed on a single silicon wafer, and then the wafer is cut into a number of smaller units called chips. These chips are arranged on substrates which are packaged in Integrated Circuit (IC) modules. The IC modules are soldered into printed circuit memory cards to form a basic component of a computer memory. During the production of monolithic chips, some of the storage cells may become defective. For example, some memory chips may incur localized imperfections which render a plurality of storage cells defective. Rather than reject an entire memory chip having some defective storage cells, it is known to utilize such a partially defective memory chip in a computer memory.
For example, U.S. Pat. No. 3,781,826 discloses a system in which partially defective memory chips are arranged on a memory array card, and logic circuitry is provided between a memory address register and the array card. The logic circuitry translates each address output from the register to prevent addressing of storage cells in defective areas of the memory chips. When an address corresponding to a storage cell in a defective area of a chip is output from the register, the logic circuitry transforms the address to that of a storage cell in a non-defective area of the chip. In this way, defective storage cells are not accessed. U.S. Pat. Nos. 3,735,368 and 3,714,637 are further examples of computer memory systems which utilize partially defective memory chips.
Although it is generally known to utilize partially defective memory chips in a computer memory system, such known systems have a shortcoming in that the partially defective memory chips are not pin-for-pin compatible with each other. More specifically, when several partially defective chips are implemented as a full-size memory chip (i.e., a memory chip having no defective storage cells) equivalent, each partially defective chip receives a separate chip select signal via a separate chip select pin, thereby preventing the simultaneous selection and output of partially defective chips. Since each partially defective memory chip contains a separate chip select pin, these memory chips are not pin-for-pin compatible with each other, and cannot be stacked to form a memory component which is the pin and functional equivalent of a single full-size memory chip.